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Digital Electronics
NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS
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INTRODUCTION
ADDER
FULL ADDER(FA)
FA using HAs
BINARY ADDER
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QUESTION (BCD to Excess-3 using ADDER)
SUBTRACTORS
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MORE QUESTIONS
SEQUENTIAL CIRCUITS
TIMING CIRCUITS

HIGHER DECODER FROM LOWER DECODERS

Q- Obtain a 4 to 16 decoder using (a) 2 to 4 decoder (b) 3 to 8 decoder

Ans: (a) we take abcd2 as the input to the decoder. Following is the diagram to design 4 to 16 decoder using 2 to 4 decoders

When we have a=0 b=0 then top most decoder is enabled and 1 is placed on the output line out of 0 to 3 based on the value of cd2

When we have a=0 b=1 then 2nd decoder from top is enabled and 1 is placed on the output line out of 4 to 7 based on the value of cd2

When we have a=1 b=0 then 3rd decoder is enabled and 1 is placed on the output line out of 8 to 11 based on the value of cd2

When we have a=1 b=1 then bottom most decoder is enabled and 1 is placed on the output line out of 12 to 15 based on the value of cd2

Hence top 4 outputs generate min terms 0000 to 0011, next 4 generates min terms 0100 to 0111, next generates 1000 to 1011 and the last 4 outputs generate min terms 1100 to 1111.

 

(b) Similarly we can obtain the circuit to obtain 4 to 16 decoder using 3 to 8 decoders Here first 8 outputs generate min terms 0000 to 0111 while next 8 generate 1000 to 1111.

 

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